rehsd

In my post Working on game music... need storage, I had started building game music and ran out of EEPROM space to store the music. Also,...

Full data reading is now working! Progress Updates posted at the bottom... I am currently trying to get an SD Card reader working with my...

I started working on some music for my game. In this video, I am using the sound card that I built for my 6502 system. All sound is being...

I've finally been able to bring together many of the components of my 6502 system to support a retro-style game. The game will be a...

Over the past five months, I have built a few 6502 computers, starting with Ben Eater's 6502 kit. See My 6502+... a little background....

I believe I have enough functionality in my 6502 system now to take a run at developing a retro-style game. So far, I have built support...

I've made some decent progress getting my FPGA VGA working on my 6502 system. My goal is to have a "smart display" to replace the current...

Below is the configuration I used to get the Xilinx Video Test Pattern Generator (TPG) working on a Digilent Cmod A7 FPGA. This is based...

Update: I have it working. See postscript at the bottom of this post. I am attempting to get the Arty Pmod VGA Demo running on a Digilent...

I made some updates to my 6502 system to get it ready for my FPGA VGA. Previously, my USB mouse took ten VIA pins (a bit of laziness on...

I am currently working on building an improved VGA circuit for my 6502 build. My goal is to offload the video processing and have better...

If you are looking to add the VGA Pmod to your Arty A7 and control output from MicroBlaze, the following are the steps I have taken to...

Continuing from my post FPGA VGA for 6502: Brainstorming... I am trying to find a decent solution to control VGA output from MicroBlaze....

I am currently brainstorming ways to add an FPGA-based VGA circuit to one of my 6502 builds. And... I have questions. :) As part of my...

I have added UART support to my VHDL 8-bit CPU, along with a Windows application that allows retrieving and setting RAM values at...

I am trying to determine why I am unable to communicate out through a UART on my Arty A7-100T. Any suggestions on how to troubleshoot...

As a continuation of FPGA VHDL Implementation of Ben Eater's 8-bit CPU - Progress Update, here's another update on my 8-bit CPU in VHDL...

I've been working on a VHDL implementation of Ben Eater's 8-bit CPU. I have VHDL modules built for the clock, registers, bus, RAM, ROM,...

Continuing my project of building Ben Eater's 8-bit CPU on an FPGA, I created the clock module in VHDL. I connected that VHDL to a...

My first attempt at getting Digilent's OLEDrgb Pmod working with an Arty A7 was unsuccessful. After a fair amount of troubleshooting and...