Researching memory map and decode logic for my 65816 build
Updated: Feb 11, 2022
For my current 6502 build, I'm using Ben Eater's design for the memory map and glue logic.
As I'm thinking about my 65816 build, I'm trying to figure out what the memory map and decode logic might look like. I have little experience setting up memory maps and decode logic, other than extending Ben's design a little bit for some additional VIAs. I found Adrien's video Memory map, address decoding to be helpful.
I have these constraints (probably missing some):
Interrupt vectors need to be in Bank 0 (first 64KB of the memory map).
Direct memory and stack memory must be in Bank 0. The specific addresses for Direct and Stack locations, within Bank 0, are configurable.
I plan to use 32K x 8 SRAM for the Bank 0 RAM.
I plan to use 512K x 8 flash (i.e., ROM).
I plan to use 512K x 8 SRAM for extended RAM.
I have no idea about I/O yet, but I plan to leave a large memory space open for it.
I am planning on 320 x 280 x 1 Byte for video. I plan to use three 32K x 8 dual-port SRAMs. This will require 1.5 Banks. I plan to leave a larger space available, in case I decide to extend the video memory in the future. (FIFOs are on my research list.)
I plan to run the processor in Native Mode. I do not plan to use Emulation Mode (other than switching at start-up from Emulation to Native).
As I understand it, using addresses beyond Bank 0 is less efficient than using addresses in Bank 0. There are likely other bank-related considerations that I fully don't grasp yet and will get to learn along the way. :)
As I will likely not get the addressing setup and decode logic right the first (second, third) time, I am going to temporarily use an FGPA for a simple circuit for the decode logic.
Below are the primary components with which I'll be starting. I will come back to video memory in the months to come; I will start with a two-line or four-line LCD display.
Here's how I'm starting to build my address map (it's an eye chart... click to view full screen):
Here's the decode logic I have so far:
And the FPGA implementation of that logic:
I can only imagine how many things are *not right* with the above. :)