FPGA VHDL Implementation of Ben Eater's 8-bit CPU - Progress Update
I've been working on a VHDL implementation of Ben Eater's 8-bit CPU. I have VHDL modules built for the clock, registers, bus, RAM, ROM, and control bits. I have these modules added to a block design as RTL modules. I also have output to an OLED display working.
Tie up loose ends in the design.
Start testing one component at a time.
Fix all of my mistakes. :)