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80286 Build #2 (Intel Basic System Configuration)

Updated: Nov 16, 2022


I am starting plans for build #2 of a '286 breadboard-based system. With this build, I hope to implement the full "basic system configuration" from Intel. I will use this running post (check back periodically for updates) to share design considerations as I get into the build.



Design Goals

In order of importance to me:

  1. Implement Intel's basic system configuration, including a 287 math co-processor.

  2. Balance simplicity with capability but give priority to simplicity.

  3. Leverage components reasonably available (and not overpriced).

  4. Leverage real-address mode exclusively (i.e., no use of protected virtual-address mode).

  5. Significantly improve my x86 assembly skills.

  6. Homegrown "BIOS" and "operating system." I use these terms lightly, as my implementation will be very basic.

  7. ...


Design Considerations, Including Suggestions from Others

  1. My initial thought was to use the same address map as build #1, where RAM sits in the first 0.5 MB of the address space and ROM sits in the next 0.5 MB. However, I have not locked into this yet and am considering different options. Possibly, I will use a pair of SST39SF010A flash ROMs. A pair of these (high & low bytes) will provide 256 KB of usable ROM, leaving 768 KB of address space for RAM (and some I/O addresses). Suggestions from others:

  2. ROM banking, freeing up more address space for RAM.

  3. Copy ROM into RAM at boot via hardware (not through assembly).

  4. Add additional latch IC for control signals from processor and PSoC (e.g., MIO, BHE, I/O enables).

  5. ...


Phased Approach

As I think through it, I might be best off approaching build #2 in a phased approach.


Phase 1
  • Basic memory map

  • RAM in first 512 KB

  • ROM in next 512 KB

  • I/O mapping with IN/OUT instructions and memory-mapped I/O (addressing to be determined).

  • Processor clock speed in the range of 4 MHz to 8 MHz

  • ...

Phase 2
  • DMA support

  • Wait states for slower devices and increased processor speed

  • Shadow ROM and possibly ROM banking, leveraging PSoC for shadow copying (e.g., counters and supporting logic).

  • ...









Schematic as of 28 October 2022
Schematic 20221029
.pdf
Download PDF • 727KB
Associated logic in PSoC









See also: Power Distribution, Clock, & Reset PCB v2 (rehsdonline.com)



As this post is getting a bit long, I will continue updates in a new post. See you there!


Continued at 80286 Build #2 (Intel Basic System Configuration), Part 2.

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