For my 286 to 386SX upgrade interposer PCB, I need to implement logic for S0# and S1# (along with a few other signals). For my 386DX build, I need to implement logic for bus control and general glue logic. I expect there are dozens of ways in which these needs can be addressed. In this post, I will try to capture some of my learnings in implementing different logic.
In my 386SX Upgrade? post, I referenced a nice reference from VLSI Technology Inc (pages 7-5 to 7-7) for logic to connect a 386SX to a 286 chipset. The sample logic code is in PALASM. I converted this code to CUPL, since I have a working toolset for CUPL. I then write this logic to a GAL.
For my 386DX system, I need bus control and glue logic. Looking an Intel's reference design documentation, a pair of PALs are used -- PAL1 and PAL2 -- for the bus control logic. Intel offers sample logic code for these PALs in ABEL and PALASM. I am also using a PSoC for other glue logic.
So Many Acronyms
ABEL-HDL, PALASM-HDL, and CUPL-HDL are three different ways to represent logic circuits... from a time long ago. Today, Verilog and VHDL are commonly used (and ABEL, PALASM, and CUPL are not).
HDL (Hardware Description Language): Specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits (Hardware description language - Wikipedia).
ABEL (Advanced Boolean Expression Language): HDL released in 1983 by Data I/O Corporation.
PALASM (Programmable Array Logic Assembler): HDL created in the early 1980's by Monolithic Memories, Inc. (MMI).
CUPL (Compiler for Universal Programmable Logic): HDL released in 1983 by Assisted Technology.
Ultimately, for me, the object is to program an IC with logic to support my 386SX or 386DX. All three of these HDLs can serve the purpose. I am new to all three, and I imagine each has its advantages and disadvantages.
As I've begun to work with these, my top considerations in selecting between these options include:
Ease of using toolsets (e.g., can it run on Windows 11?)
Quality of those toolsets
Verilog is another HDL and is commonly used today. When I design logic in the PSoC Creator software, I believe it is using Verilog behind the scenes (I simply use the graphic layout functionality and do not directly utilize Verilog). Verilog - Wikipedia
VHDL (VHSIC Hardware Description Language) is another HDL and is also commonly used today. While I am not using VHDL in any of my 386 projects (at least not yet), I have used some VHDL in other projects. VHDL - Wikipedia
Whichever HDL I use, I need to write that logic to some form of a programmable device.
PLD (Programmable Logic Device): An electronic component used to build reconfigurable digital circuits.
PAL (Programmable Array Logic): Consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.
PLA (Programmable Logic Array): Has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. PLAs differ from PALs in that both the AND and OR gate planes are programmable. Programmable logic array - Wikipedia
GAL (Generic Array Logic, or Gate Array Logic): Was an innovation of the PAL and was invented by Lattice Semiconductor. The GAL was an improvement on the PAL because one device type was able to take the place of many PAL device types or could even have functionality not covered by the original range of PAL devices. Generic Array Logic - Wikipedia
CPLD (complex programmable logic device): A programmable logic device with complexity between that of PALs and FPGAs.
PSoC (Programmable System on a Chip): A family of microcontroller integrated circuits by Cypress Semiconductor. These chips include a CPU core and mixed-signal arrays of configurable integrated analog and digital peripherals.
FPGA (Field-Programmable Gate Array): An integrated circuit designed to be configured after manufacturing. These are the most capable device listed on this page. Field-programmable gate array - Wikipedia
For my 386-related work, I will likely use PAL, GAL, and PSoC devices.
For PALs, I am trying to keep my work in WinCUPL, especially if using CUPL-HDL. If using ABEL-HDL, I will use ABEL Design Environment (an old DOS application).
For GALs, I will use Digital and/or WinCUPL. I have previously posted on programming GALs using Digital. See Using GAL22V10 Programmable Logic Devices (rehsdonline.com).
For PSoCs, I will use the graphical environment offered by the vendor, Infineon Technologies (formerly Cypress). I have previously posted about PSoCs. See Using PSoCs for Rapid Prototyping (rehsdonline.com).
More to Come
As I work through the logic for my 386-related projects, I will post the code (e.g., ABEL, PALASM, CUPL) to my GitHub, along with the resulting files that are ready to be programmed to the devices (e.g., compiled JEDEC files).
Suggested Edits, Additions?
If you have suggestions on how to improve this page as a helpful reference, please let me know! Thanks!!
386DX PAL1 in PSoC
In case you are interested in seeing the 386DX PAL1 converted to logic gates in a PSoC, check out the following PDF.
VTI_ComputerProducts_1989_text.pdf (Section 7)