As a follow-up to Brainstorming... Video Card for 286 System, I am now working to get my VGA card working in my 80286 system.
Initial fire up is looking promising. First... no magic smoke. Second, the '286 system still boots with the VGA card installed. Third, the monitor is syncing to the proper resolution and frequency, and the content matches what I would expect for uninitialized video RAM.
I now need to add some assembly code to write to the video RAM and see if I can get the desired output (e.g., clearing the screen, or a simple test pattern).
I built a handful of simple VGA initialization routines, to test the primary colors. Here's an example:
vga_init_red:
; Video RAM (128 KB) = 0xA0000-0xBFFFF
push ax
push bp
push si
mov bp, 0xfffe ; offset within segment
; (i.e., 0xffff down to 0x0000)
mov si, 0xb000 ; segment start
; (i.e., 0xb000 as top)
mov es, si
.offset:
mov word es:[bp], 0xe0e0 ; write color
; rrrgggbb, 0xe0=full red
sub bp, 2
cmp bp, 0xfffe
jnz .offset
sub si, 0x1000
mov es, si
cmp si, 0x9000 ; if equal, finished 128 KB
; of video RAM
jnz .offset
.out:
mov ax, 0xf000 ; Read-only data in ROM at
; 0x30000 (0xf0000 in address
; space 0xc0000+0c30000).
; Move es to this by default
; easy access to constants.
mov es, ax ; extra segment
pop si
pop bp
pop ax
retAfter posting the above video, I added bus resistors to the video card. I used a 3.3K pull-down on the video card's internal bus and a 1K pull-up on the video card's external bus (the system external bus). I also adjusted the CLK and PCLK inline resistors, moving the PCLK resistor down to 33 and the CLK up to 100. With these changes, the system is running (with the video card) at 18 MHz (9 MHz effective processor internal clock).
I have completely removed all vertical banding by swapping out the 74HC161 ICs with 74LS161 ICs. My original schematic had LS, but I thought HC would be fine; they were not.
Schematic Issue
While working on font rendering assembly code, I was running into what I thought was a coding issue. It ends up that it's a hardware issue. In the image below, I am rendering out a pair of contiguous vertical pixels, then moving to the right and rendering another pair of contiguous vertical pixels. I do this for both the upper VRAM and lower VRAM. In the image, the lower set of pixels is how the upper set should look. Unfortunately, I am getting an extra, slightly lower pair of pixels in the upper set.
So, looking at the schematic for the VRAM, below, I noticed that I missed updating one of the address lines. Instead of VA11, I have a second VA10. This affects the upper portion of the screen (lower 64K of VRAM), and only for odd addresses.
Unfortunately, the traces connecting to the pin are on the top side of the PCB, but under the PLCC socket. I plan an attempt to modify the existing card by desoldering the PLCC socket, cutting the traces accordingly, and running bodge wires as needed.
After corrections, this issue looks to be resolved. Now, back to assembly coding...
Code used in the above video is available at x86/286-related/WorkingCode/g2_20221221 at main · rehsd/x86 · GitHub.
Current Schematic
PLD Config
More to come...