Updated: Feb 27, 2022
Previously, I have been able to get ROM and RAM working together in my 65816 system, as seen here. However, I have had some sporadic issues and have not been able to pin down the root cause.
Symptom: Without the RAM enabled (e.g., RAM CS# tied high), ROM reads and code processing look fine. When the RAM's CS# line is controlled from the EEPROM or an address line, ROM reads fail to work properly (and therefore the code on the ROM fails to run).
Through the troubleshooting process, I have moved my build to solderable prototype boards. I have removed the FPGA for decode logic and gone to an EEPROM; I have even temporarily removed the EEPROM from the circuit and am using very basic decoding based off an address line (A15) -- assuming either RAM or ROM are active. I have an additional RAM chip on the memory board, but I have its CS# tied high.
Here's my mess of a system right now:
More importantly, here's the schematic (click to view full screen). Note: I do have power and ground to the inverters even though it is not shown on the schematic.
Below is a video showing the behavior when RAM is not enabled followed by a reset when RAM is enabled. I first show behavior with RAM is disabled. At approximately 1:30, I show the behavior when RAM is enabled (ROM and RAM control with A15 and an inverter).
Things that come to mind (but I have not been able to resolve the issue based on these ideas):
Is this some sort of a timing issue?
I have tried a dozen different configurations to manage the WE#, OE#, and CE# signals of the RAM and ROM. It seems like the RAM and/or ROM are not entirely recognizing the low/high of the enable signals. Is there an issue related to how I am managing the enable signals (e.g., open drain issue)?
Am I using chips that are not compatible, as far as TTL vs. CMOS?
Likely, I'm missing something obvious and will feel silly once the issue is pointed out to me. I could use a fresh set of eyes on this. If you have suggestions, please let me know! Thank you!!
Relevant Data Sheets
Here's the test code that I'm running:
Thank you to u/gfoot360 and Frédéric Segard for suggestions. I have qualified the OE#, WE#, and CS# signals with the clock. I also added pullups to ABORTB, IRQB, and NMIB on the W65C816S. The following schematic has been updated to reflect these changes. I also added the bus resistors to the schematic.
Updated system picture and runtime logging:
I have completely removed the RAM board from the circuit. I added a new breadboard with a single 32K RAM chip. I verified continuity for all address and data pins to the RAM.
I have swapped out both the ROM and 32K RAM chips with new chips.
I have gone back to my breadboard version and have set it up based on the most recent schematic above. I now have two systems to compare. I think I'm going to need to dig into timings of the chips I'm using and draw it out like Adrien has been doing in his videos. I notice he's running into a latching issue in his most recent video, and he suspects his HCT chip isn't fast enough.
As I'm looking at timings, I wonder if the 74AC245 buffer is latching too quickly. I plan to experiment with delaying the inverted clock.
I have yet to find the source of the issue. I am still digging into timings, and I've started to capture a timing diagram. This is what I have so far:
Also, I have ordered a full set of 74HC chips. Looking at my WDC single-board computer, all the logic is using the HC series. I'm curious to see if I get a different result with HC chips.
I switched my CLK source over to a dual D-type flip-flop, 74ALS74A, to remove any potential delay in the inverted clock.
While I wait for my 65816 prototyping PCBs to show up, I decided I would try building a more condensed version of the 65816 system, in case the length of the wiring was an issue. I am using HC family ICs for the '573, '245, '14, and '00. On the upside, I can now reproduce the exact same issue on three different builds. :(
On build 3, I have started looking at timings in more detail. Here's CLK (yellow) and CLK# (magenta). I've been driving my three builds off a simple 555 circuit (at ~1Hz) through a 74HC14 to clean it up a bit. Note that earlier on build 2 I tried a 74LS74 flip-flop. Below... 30ns is way too slow. I have some 74AC74 flip-flops on order to clean up the clocks.
I might have finally made some progress. I have been able to manually add some timing delays in certain areas of the circuit, using inverters. I am trying to configure delays based on the timings of the W65C816SXB board. With these delays, the ROM is reading correctly, even with the RAM chip fully connected. I might try building out the decode logic to exactly mirror the W65C816SXB (rather than using the current PLD for decode logic). I will continue this work on my 65816 proto board, which should arrive in the coming week or so.
I am now using my 65xxx proto board, which is great. I can now better focus on timing issues, chip selection, etc.
I am going to try a slightly different family of chips. One thought that I have is the DM74AS573N I'm using isn't the best choice. I have some CD74AC573E ICs incoming. I am also going to switch most of the logic over to the AHC family. I also have an SN74ACT245N coming, but I don't think my current 74AC245PC should be an issue there.
Additionally, I ordered a couple of additional W65C816S processors. I am working out of a batch of five (from the same China source). I believe three of them are bad, so I'm questioning the other two. Long shot, but I thought I better try an alternate source.
Further Review of Signal Voltages Levels
Timing might not be my (only) issue at this point. I spent some time reviewing input/output working voltages of all the ICs I'm trying to use. It's not all lining up, lol. Here are the ICs that I've been trying to use up to this point:
The problems I see with the above set:
The 74AC245PC requires 2.5V for a high input signal, but my SRAM and Flash only output 2.4V for high.
The DM74AS573 outputs 3.3V for a high, but the '816 needs 4.0V for a high input.
To address the voltage issues:
I will be swapping my 74AC245PC out with the ACT version. It only requires 1.5V for a high input, so my SRAM and Flash using 2.4V for high will be good.
I will be swapping my DM74AS573 out with an DM74AC573. It outputs 4.99V, so my '816 will be good with that.