W65C265S Parallel Interface Bus (PIB)
- rehsd
- 2 days ago
- 4 min read
As I've been working on my W65C265S single-board-computer (SBC) project (see rehsdonline.com/post/w65c265s-single-board-computer), one of the greater mysteries is the parallel interface bus (PIB). I've found limited information about the PIB, other than some basics in the '265 data sheet. I'm hopeful to get the PIB implemented in the latest phase of my '265 SBC project. Here, I will collect information that should be helpful in my goal of implementing PIB for a dual-265 SBC. As of this writing, I have an updated PCB designed that might support PIB.
The general design intent is to have a primary '265 microcontroller with a secondary "co-processor" for audio-visual tasks (I'll refer to the secondary MCU as my AV-265). These tasks include managing the VGA output and audio output (using a pair of YM2149 programmable sound generators). The primary controller can submit simple requests to the AV-265 and continue on with other work, while the AV-265 grinds through screen draws and playing audio.
As I start this blog post, my latest schematic is microcontollers/W65C265S/65265 schematic 20260107.pdf at main · rehsd/microcontollers · GitHub.
This post will be updated as I work through the PIB design of my SBC.
Some of the information here is speculation, or me "reading between the lines" due to limited documentation. If you see anything that is incorrect, please let me know so that I can correct it.
PIB Information from Western Design Center (WDC)
Here, I am capturing information that WDC has published on the PIB. In the subsequent section, I will capture my interpretation and implementation.
3.21 Parallel Interface Bus (PIB)
2.10 Parallel Interface Bus (PIB)
Parallel Interface Registers
Parallel Interface Bus Enable Register
Parallel Interface Bus Flag Register
W65C265S 100 Lead QFP Chip Carrier Pinout
Communication Register Map
Memory Map
Edge Interrupt Enable Register (EIER)
Edge Interrupt Flag Register (EIFR)
Native Mode Priority Encoded Interrupt Vector
Address: 0xFF9C,D
Label: IRQPIB
Function: Parallel Interface Bus (PIB) Interrupt
Information from Other Sources
Placeholder... not much out there!
If you know of additional information sources, please drop me a note! Thanks!
My Implementation
Here, I will share my interpretation and implementation.
Here is what I am thinking for connectivity of the two '265 MCUs.
Above, IRQ7 and AV_IRQ7 go into independent CD4068 ICs (8-input AND) and then into the IRQB line of the related '265.
Below, I list considerations related to the connections in the image above.
Pin | PIB Use | Other Functions |
P42 | PIIB (Parallel Interface Interrupt) The PIB interrupt output to the "host" is generated on the Parallel Interface Interrupt (PII) pin. The "host" interrupt is suggested to be received on the IRQ level interrupt input pin of the "host" processor. | None |
P43 | PIWEB (Parallel Interface Write Enable) / PIWRB (Parallel Interface Write Register?) The Parallel Interface Write Enable (PIWEB) input pin is used with the Parallel Interface Chip Select (low active)/Parallel Interface Chip Select (high active) (PICSB/PICS) signal to transfer data to and from the Parallel Interface Register selected by the Parallel Interface Register select (PIRSx) input pins. When PIWEB and PICSB are configured by the Parallel Interface Bus Enable Register bit 1 (PIBER1=0), then the PIB interface is compatible with WDC microprocessor WE- logical operation with the chip select PICSB input. The use of PIWEB and PICS are configured by PIBER1=1. | FA15 Used on SXB for external ROM bank select. |
P44 | PICSB (Parallel Interface Chip Select low active) / PICS (Parallel Interface Chip Select high active) PIRDB (Parallel Interface Read Data?) See notes on P43. | AMS Used on SXB for external ROM bank select. |
P45 | PIRS0 (Parallel Interface Register Select) | None |
P46 | PIRS1 (Parallel Interface Register Select) | None |
P47 | PIRS2 (Parallel Interface Register Select) | None |
P50 | PID0 (Parallel Interface Data bit 0) | DTRB0 |
P51 | PID1 (Parallel Interface Data bit 1) | DSRB0 |
P52 | PID2 (Parallel Interface Data bit 2) | DTRB1 |
P53 | PID3 (Parallel Interface Data bit 3) | DSRB1 |
P54 | PID4 (Parallel Interface Data bit 4) | DTRB2 |
P55 | PID5 (Parallel Interface Data bit 5) | DSRB2 |
P56 | PID6 (Parallel Interface Data bit 6) | DTRB3 If connected to the FT232, and using UART3, this may be an issue. If P56 is connected to the FT232 (like on the SXB), does the trace need to be cut (no inline resistor on the SXB to remove)? |
P57 | PID7 (Parallel Interface Data bit 7) | DSRB3 If connected to the FT232, and using UART3, this may be an issue. If P57 is connected to the FT232 (like on the SXB), does the inline resistor (R9 on the SXB) need to be removed? |
While I have a PCB designed and ready to be ordered using the above connectivity, I am somewhat guessing at this connectivity. Given that, I am looking to test this using my first revision of a '265 SBC and a WDC W65C265SXB. I have recently moved all peripherals off of ports 4 and 5 to free up these ports for PIB. I'm starting with this...
Above, the green board is my custom PCB (round one), and the red PCB is WDC's W65C265SXB. On the right side, I have a versatile interface adapter (VIA) to support PS/2 keyboard data input and 1602 LCD output.
Next up, I need to connect the two PCBs and begin assembly code work.
More to come!